How do I make sure my board has maximum test coverage?
We have produced a set of Design For Test (DFT) guidelines which explain what you need to take into consideration when designing your board, to make sure that as much of your board as possible is testable using JTAG.
Which CAD Netlist formats can XJTAG import?
Our recommendation is that customers use ODB++ board data because this contains both netlist and layout information and almost all CAD tools can generate ODB++. However, if you do not have ODB++ you should be able to use any ASCII netlist.
XJTAG supports over 100 netlist formats that the system automatically parses, identifies and accepts. These include RINF, Protel, PADS-PCB, Cadence Allegro, P-CAD, Genrad, BoardStation (Mentor), Zuken, Protel V2, EDIF 2 0 0 and many others.
If you have an ASCII format netlist that is not recognised, please contact XJTAG Support and we will be happy to convert it to a format that works and add a parser to a future release.
More about netlist formats on the XJTAG Blog.
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