As DDR5 memory becomes more widely available, being incorporated in more products, one question we are frequently asked is: can I run JTAG tests on DDR5? The simple answer is – yes.
DDR5 is the next variation of dynamic RAM operating at higher speeds and lower voltages and as such is not interchangeable with earlier generations of DDR DRAM. The slightly lower operating voltages of DDR5, 1.1V compared to 1.2V for DDR4, results in a useful power reduction. DDR5 also offers significantly higher data transfer speeds, ranging from 4000 to 8800 MT/s compared to DDR4’s range of . Most notably, DDR5 has four times the memory density per die, with DDR4 ranging between 4 Gb to 16 Gb compared to DDR5’s 16Gb to 64 Gb.
JTAG testing of memory
When performing JTAG tests, our goal is to ensure that the PCB has been correctly assembled. We check that the proper components have been used, that they are functional, and, most importantly, that there are no short-circuit or open-circuit faults on the board. When we perform tests with DRAM we use JTAG boundary-scan enabled devices on the board to exercise the address and data busses to write values to memory and then read them back. By using carefully selected sequences of test patterns we can not only detect if a fault exists but also diagnose the location of the fault.
DDR5 Memory Modules (DIMMs) do not have the TEN (Test ENable) pin on the connection to the mother board and so must be tested in a similar way to earlier memory types, however if you are designing a board with DDR5 mounted directly on the PCB, we recommend that you wire the TEN pin to either a JTAG enabled I/O pin or to a test header so the device can be put into connectivity test mode.
What does the connectivity test mode do?
When placed in Connectivity Test (CT) mode the device pins are divided into an input set and an output set. Between these pins are a set of asynchronous logic gates, defined in the JEDEC® DDR5 specification. By sending different signals to the input pins and monitoring the output pins we can quickly establish if there are any shorts or opens. CT mode is designed specifically to work with boundary-scan devices allowing test patterns to be entered on the test input pins in parallel and read from the outputs in parallel. This is quicker than writing patterns to the memory and reading them back.
Other DDR types
LPDDR5 – Low Power DDR does not have a TEN pin and must be tested the same way as DDR3 and earlier.
GDDR6 – Graphics DDR – is not, as the name might suggest, a successor to DDR5; it actually predates it. GDDR6 does however have a test mode which enables the pins to be driven in parallel then the received values read back serially, enabling connectivity to be tested relatively simply. This is a form of boundary-scan, but should not be confused with 1149.1/JTAG.
Conclusion
In summary, DDR5 memory can be quickly and reliably tested using JTAG, either by using the same process used in DDR3 (memory write/reads to test connectivity) or by using the TEN pin to place the device into connectivity test mode similarly to DDR4. Devices offering access to the TEN pin will enable faster tests.
DDR5 device models are available now, please contact us if you have any devices you would like to test which aren’t yet available in the library.
Other resources
What is JTAG?
And how can I make use of it?
High-Level Guide to JTAG
See what JTAG can do
Technical Guide to JTAG
A low-level look at how JTAG is implemented