FAQ

XJTAG is an innovative boundary scan software and hardware suite that enables rapid testing, debugging and programming of complex embedded electronics. XJTAG products work with the JTAG test access protocol – built into FPGAs, CPLDs and most CPU devices – that enables testing interconnects on printed circuit boards.

XJTAG’s mission is to help engineers to complete PCB debug and testing quickly and easily, enabling customers to focus on developing better products faster and manufacturing them more cost-effectively.

See what world leading companies are saying about the XJTAG system.

None. JTAG, also referred to as Boundary Scan, is a test access protocol that is embedded into many chips. It is a set of IEEE standards (1149.x) that allow JTAG-enabled ICs from any manufacturer to be connected and accessed via a simple 4-signal interface.

By controlling devices from the inside, XJTAG’s Boundary Scan products give test access to thousands of circuit nodes on your circuit board, including pins under Ball Grid Array (BGA) devices, which are inaccessible to conventional probes.

JTAG is also used for processor debug/emulation and In-System Programming.

Read more: What is JTAG and how can I make use of it?

In order to test a board using boundary scan you will need the netlist for the board and the BSDL file(s) for the JTAG compliant devices on the board. The methodology nature of boundary scan testing is to compare the data returned from a Device Under Test (DUT) with the design to which that board was built. The netlist gives us the information about the design and the BSDL file gives us information about which parts of that design can be controlled / monitored using boundary scan.

The XJTAG test system uses this information to generate a set of ‘test vectors’ that will stimulate the board in such ways that we will be able to verify as much of the manufacturing integrity of the board as possible. This test coverage extends beyond just the JTAG-compliant devices on the board by proving that the JTAG enabled devices can interact with those devices that don’t have any JTAG capability.

Not all devices have JTAG capability. Typically processors, DSPs, FPGAs, CPLDs, some Ethernet devices and QDR RAM have JTAG interfaces, along with some ASICs. Devices such as RAM and flash typically do not have this capability.

For JTAG enabled devices XJTAG uses their capability as its control mechanism, in the same way that a bed-of-nails machine uses a test fixture as its control mechanism. We use those devices to drive the nets to which they are connected, and to monitor the values of those nets while tests are running.

It is often possible to use JTAG enabled devices to interact with the functionality of non-compliant devices in order to give the best possible test coverage on a DUT. Consider the nets that run between a processor and a RAM device. These nets can be tested for short circuit faults by our automatic interconnection test – the system will stimulate one net and check to see if the driven value is read on any of the other nets. However this type of test cannot check for open circuit faults at either the processor or the RAM. Nevertheless, a test that writes data into the memory array of the RAM and then reads values back can be created, and this test can also check for open circuit faults at both devices.

There are situations where type of testing can go further – for example external connectors can often be tested by connecting a loopback cable and then sending and receiving data to verify the operation of nets which have no direct connection to the JTAG enabled devices on the board.

Unfortunately this is not possible. JTAG boundary scan is something that the device manufacturer has to add to the device, it cannot be added at a later stage.

XJTAG uses the information contained in a BSDL file to work out how to access a device in the JTAG chain. Boundary Scan Description Language (BSDL), based on VHDL , is used to describe how JTAG (IEEE 1149.1) is implemented in a particular device.

These files are often available for download from the website of the component manufacturer. Some manufacturers require an NDA in order to release these files but most make these files publicly available.

Here are some links to BSDL files from a range of device vendors.

Whilst the IEEE 1149.1 (JTAG) standard defines certain standard cell types for use in JTAG devices, some manufacturers use non-standard cell types, in which case additional information is needed by XJTAG to use the devices. Follow the link above to learn how to identify such devices and supply the additional information to the XJTAG system.

JTAG systems can do limited testing when it comes to analog devices – JTAG is a digital technology. A JTAG pin can be set high or low but the voltage driven onto the net is defined by the device being used. Similarly the JTAG device can capture (read) a digital value of 1 or 0 but it does not report whether a 1 is caused by a voltage of 3.3 V or 2.8 V.

Boundary scan allows checking whether a resistor is connecting two nets together, providing there is a mechanism to test for open-circuit faults on each side of the resistor. If for example the resistor is connecting a processor to a RAM then we will only be able to verify the connections to the RAM if the resistor is in place. However it would not be possible to use boundary scan to check whether it is a 0R resistor, a 100R resistor or even a 1K resistor as the JTAG compliant device would be able to drive signals through all of these values.

Similarly if there is a pull resistor on a net the undriven net’s digital value can be tested to be correct, depending on whether it is a pull-up or a pull-down. However the value of the resistor cannot be determined, so a 1K resistor would look the same as a 4.7K resistor to a boundary scan test.

Most capacitors on a Device Under Test are found in the power supply sections of the board, where typically JTAG access is poor. Others may have little effect on the low speed testing that boundary scan tests typically carry out. However some testing can be performed on inline coupling capacitors if the JTAG compliant devices on both sides of them support the newer 1149.6 JTAG standard. If full testing of these components is required then boundary scan testing should be combined with ICT for best results.