Clearing Xilinx FPGA configuration to allow boundary scan testing

When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device, as described in the Application Note “Working with configured Xilinx and Altera devices“. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing boundary scan testing to occur without any problems.

A second issue that can affect boundary scan testing with FPGAs is that they contain pull resistors. Depending on the design, these may be enabled when the FPGA is unconfigured as well as when it is configured. If these internal resistors are enabled on nets that contain pull resistors mounted on the board, two potential problems can occur:

If the internal resistor and external resistor pull in opposite directions, the boundary scan tests may not be able to test the external pull resistor if it is weaker than the internal pull resistor.

If the internal and external resistors pull in the same direction, a fault with the external resistor may not be detected because the internal resistor may mask the fault.

By setting the correct configuration options it is possible to disable these internal pull resistors when generating a ‘blank’ FPGA image.

Blank don’t clear

Although clearing the FPGA to an unconfigured state may help resolve the problems encountered when using a configured device, it may not always help, such as with internal pull resistors. There can also be problems with the board trying to re-configure the FPGA once it is returned to its unconfigured state. Therefore, although returning the FPGA to an unconfigured state may have the desired effect, using a ‘blank’ FPGA image should achieve better results and be more reliable.

Creating a ‘blank’ FPGA image using Vivado

To create a suitable FPGA image for Xilinx FPGAs supported by Xilinx Vivado software:

Open Xilinx Vivado version 2016.3 or newer.

Create a new RTL Project, selecting the required target FPGA. Do not add any sources, existing IP or constraints to the project.

Run the script in this zipped file. The easiest way to do this is from the Tools > Run Tcl Script… menu, and then select CreateBlankVivado.tcl.

Wait for the script to complete – it should automatically generate the necessary source code, build the image and generate a file called blank_*.svf in the project directory, where * is the FPGA device.

Copy this generated file into your XJTAG project directory and then use it with the RUNSVF XJEase command to configure the FPGA as part of your XJTAG project.

Creating a ‘blank’ FPGA image using ISE Design Suite

To create a suitable FPGA image for Xilinx FPGAs supported by ISE Design Suite:

Create a new project in Xilinx ISE Project Navigator. Specify the correct target FPGA type, and leave all other parameters at their default values.

Add both top.v and top.ucf (below) to the project using the menu item Project > Add Source.

File top.v:

module top(
    output wire BUS_IO
);

// synthesis attribute s of BUS_IO is yes;
assign BUS_IO = 'hz;
endmodule

File top.ucf:

# Signals listed here will not have their pull resistor controlled by   
# the configuration option "Unused IOB Pins".
#   Append "| PULLUP" to enable a pull up resistor on the pin.
#   Append "| PULLDOWN" to enable a pull down resistor on the pin.
#   Appending neither will leave the pin floating with no pull resistor.

NET "BUS_IO" LOC = "A4" | IOSTANDARD = "LVCMOS33";

Make sure that the pin specified by LOC in top.ucf is a valid IO pin on the FPGA.

Select top in the Hierarchy, which should then list the available processes in the lower part of the screen. From here, right click on Generate Programming File and select the Process Properties… item. In this dialog make the following changes:
1. In the General Options category, select Enable BitStream Compression. This is not essential, but will reduce the time taken to configure the FPGA.
2. In the Configuration Options category, change Unused IOB Pins as required:
  - Float will disable the internal pull resistors for all pins not specified in the top.ucf file. This is normally the best option to get the best test coverage of pull resistors on the board.
  - Pull Down or Pull Up will enable the internal pull down/up resistors for all pins not specified in the top.ucf file. This is not normally recommended because it will potentially make the testing of external pull resistors fail. Additionally, it may mask some faults with external resistors (e.g. if Pull Up is enabled, it would mask problems if an external pull up resistor is missing).

Double click on Generate Programming File to build the FPGA image.

Once the FPGA image has built, double click on Configure Target Device to open ISE iMPACT:
1. Create a new project – it will try to detect a cable, but it does not matter if this fails.
2. Add a Xilinx Device to the project, using the FPGA image file called top.bit that has just been generated.
  Note: there is no need to add any other devices to the project, even if there are other devices on your JTAG chain, because XJTAG will handle this.
3. Use the menu item Output > SVF File > Create SVF File… to specify the name of the SVF file to generate.
4. Right click on the image of the FPGA, and select Program.
5. Once this has completed, use the menu item Output > SVF File > Stop Writing to SVF File to close the SVF file.
6. The required SVF file to be used with the XJEase statement RUNSVF has now been generated. If the FPGA image ever gets rebuilt, a new SVF file can be created by repeating steps (c) to (e) above.

In some cases, it may be necessary to enable some pull-up/down resistors whilst leaving other pins floating. To configure different pins with different pull resistor settings, do the following:

Determine the most common setting across all IO pins on the device (i.e. pull up, pull down or float) – change the Unused IOB Pins configuration option to this setting. It does not matter which of these is chosen, the intention is to minimise the number of pins that need to be explicitly referenced in the subsequent steps.

Count the number of pins that need a setting that is different to the Unused IOB Pins setting chosen, and change the line in top.v to
```
output wire [n - 1:0] BUS_IO
```
replacing ‘n’ with the number of pins to configure

Update top.ucf so there is the following line for each pin, updating LOC accordingly:
```
NET "BUS_IO[k]" LOC = "A4" | IOSTANDARD = "LVCMOS33";
```
On each line put a sequential number for ‘k’, ranging from 0 to (n – 1). This line as it is would leave the pin floating. If the pin needs to be pulled up, append | PULLUP before the semicolon; alternatively append | PULLDOWN for a pull down.

SVF File TCK Frequency

SVF files produced by iMPACT tend to use a TCK setting of 1 MHz, set using the FREQUENCY command within the SVF file. In many cases the JTAG chain on a board can run at a higher frequency than this, and so reduce the time taken to run the SVF file. The XJTAG project TCK frequency setting does not override this setting in the SVF file, so if an SVF file takes a long time to run then this may be the cause.

Removing the FREQUENCY command within the SVF file is not sufficient to get the file to work at other frequencies because, by default, they also include delays derived from the TCK frequency. From within iMPACT it is, however, possible to generate SVF files that can be run at any TCK frequency. The relevant setting can be found via the Edit > Preferences… menu item. In the Preferences dialog that appears select the category iMPACT > File Generation Controls and then enable Use Absolute Time in SVF File. SVF files generated with this enabled no longer include the FREQUENCY command, and will run at the TCK frequency specified in the XJTAG project.

Xilinx Spartan 3 – a special case!

With the original Xilinx Spartan 3 family of FPGAs (not the subsequent Spartan 3A or Spartan 3E families), configuring the FPGA with all pins set to Float has been found to significantly increase the device’s current consumption. Therefore, to get the best test coverage whilst avoiding this problem, the ‘blank’ FPGA image for these devices should float pins that are connected to external pull resistors but enable the internal pull resistors on all other pins.