Xilinx Support Information

[vc_row][vc_column width=”3/4″][vc_column_text]Welcome to the XJTAG Xilinx support section. Here you can find information about designing, testing and programming your board using boundary scan (JTAG) and the XJTAG tools.

Designing boards with JTAG-enabled Xilinx devices

By designing your board with testability in mind, you can greatly increase its test coverage when it come to manufacture. With this in mind, XJTAG has produced a set of design for test guidelines to help you in this process.

Testing your board with XJTAG

With just the BSDL files for your JTAG devices, you can view and control all the pins on those devices using XJAnalyser. Add in the netlist and you’re ready to run the XJTAG interconnect test, as well as testing the non-JTAG devices on your board using XJDeveloper.

Programming Xilinx devices over JTAG

Use SVF and STAPL files to program JTAG-enabled devices. These can be run with either XJAnalyser or XJDeveloper.

For More Information…

Contact us to find out more about testing your Xilinx device.

See also our Blog and introduction to using JTAG.[/vc_column_text][/vc_column][vc_column width=”1/4″][/vc_column][/vc_row]